The present invention relates to a semiconductor device having a so-called super junction structure.
As a typical semiconductor device which achieves a high breakdown voltage and a large current capacity, there is a power MOSFET (Metal-Oxide-Semiconductor Field-Effect Transistor). A power MOSFET of the type which allows a current to flow between a pair of electrodes formed on both surfaces of a substrate is called a vertical power MOSFET. Vertical power MOSFETs are widely used as switching devices and the like with a low on-resistance.
Vertical power MOSFETs are designed to have a predetermined breakdown voltage depending on the intended use. The term “predetermined breakdown voltage” herein used refers to a drain-source voltage obtained when a local electric field exceeds a critical value in some region of a device and a breakdown occurs. In general, there is a trade-off relationship between the breakdown voltage and the on-resistance. Accordingly, if a certain level of breakdown voltage is to be obtained, there is a limit to the reduction of the on-resistance.
In a vertical power MOSFET of related art, the breakdown voltage is determined by a p/n junction between a base region and a drift region (drain region with a low impurity concentration). In this regard, dependence of a theoretical minimum on-resistance on a breakdown voltage (referred to as “Si limit”) has been known.
In recent years, as a technique for reducing the on-resistance in vertical power MOSFETs beyond the Si limit, a so-called super junction structure (SJ structure) has been proposed. Referring now to FIG. 7, a basic structure of a vertical power MOSFET having the SJ structure will be described. FIG. 7 is a cross-sectional view showing a main part of the vertical power MOSFET.
A MOSFET 500 shown in FIG. 7 includes:
a first-conductivity-type semiconductor substrate 501;
a semiconductor layer 601 which is formed on one surface (upper side of FIG. 7) of the semiconductor substrate 501;
an interlayer insulating film 610 which is formed on the semiconductor layer 601;
a source electrode 611 which is electrically connected to the semiconductor layer 601 through a contact hole formed in the interlayer insulating film 610;
a gate insulating film 606 and a gate electrode 607 which are formed within a trench formed from the upper surface of the semiconductor layer 601; and
a drain electrode 612 which is formed on the other surface (lower side of FIG. 7) of the semiconductor substrate 601.
The semiconductor layer 601 includes:
a first-conductivity-type drift region 602;
a second-conductivity-type base region 603 which is formed on the drift region 602;
a first-conductivity-type source region 604 which is formed at an upper layer portion of the base region 603; and
a second-conductivity-type column region 605 which is formed in a columnar shape within the drift region 602.
In this example, the semiconductor substrate 501 is n+ type; the drift region 602 is n type; the base region 603 is p type; the source region 604 is n+ type; and the column region 605 is p type.
Within the semiconductor layer 601, a parallel structure (p/n junction structure) is formed in which the first-conductivity-type drift region 602 and the second-conductivity-type column region 605 are formed in parallel in the substrate surface direction.
In the SJ structure, the amount of donor impurity in the drift region and the amount of acceptor impurity in the column region are set to be substantially equal to each other. As a result, the charge in the drift region is balanced with the charge in the column region (charge-balanced condition), thereby maximizing the breakdown voltage. Under the charge-balanced condition, when a reverse bias voltage is applied between the drain and source electrodes in the OFF state of the device, a depletion layer extends uniformly in the lateral direction from the p/n junction between the drift region and the column region. This facilitates connection between adjacent depletion layers. When the entire SJ structure is depleted and becomes a single depletion layer, equipotential surfaces are formed at substantially equal intervals and in substantially parallel to each other, thereby maximizing the breakdown voltage. At the stage of designing the SJ structure, the impurity concentration of the drift region can be increased under the charge-balanced condition (in the state where the breakdown voltage is maximized). This leads to a reduction in drift resistance and a reduction in on-resistance.
Further, in the case of designing a semiconductor chip of a power MOSFET, it is important to achieve a high breakdown voltage so as to prevent breakdown of the device due to concentration of an avalanche current in an outer peripheral region of the chip, even when an excessive inductive load is applied to the device. To achieve this, it is necessary to set the breakdown voltage of the outer peripheral region to be higher than the breakdown voltage of an element forming region (cell region) in which at least one MOSFET is formed.
As means for increasing the breakdown voltage of the outer peripheral region, there is proposed a structure in which a repeated structure of a columnar p/n junction, which is one of the characteristics of the SJ structure, is extended to the outer peripheral region.
Japanese Unexamined Patent Application Publication No. 2001-298190 and US Patent Application Publication No. 2001/0028083 which is based on Japanese Unexamined Patent Application Publication No. 2001-298190 disclose a structure in which a repeated structure of a columnar p/n junction similar to that of the element forming region is formed in the outer peripheral region, and the impurity concentration of the outer peripheral region is set to be equal to or lower than that of the element forming region. This structure facilitates depletion of the outer peripheral region at the level equal to or higher than that of the element forming region, thereby improving the breakdown voltage.
FIG. 19 of Japanese Unexamined Patent Application Publication No. 2001-298190 and FIGS. 17 and 18 of US Patent Application Publication No. 2001/0028083 disclose a structure in which the same repeated structure of a columnar p/n junction (specifically, a repeated structure of an n-type drift region (20a) and a p-type column region (20b)) is formed in each of an element forming region (122) and an outer peripheral region (20). On the element forming region (122) side of the outer peripheral region (20), annular shallow p-type regions (20c) having an impurity concentration higher than that of the column region (20b) are formed so as to surround the element forming region (122). A field insulating film (23) for surface protection and stabilization is stacked on the semiconductor layer in the outer peripheral region (20). The column region (20b) is also formed in a region outside the annular shallow p-type regions (20c). In this region, the upper end of each column region (20h) is in contact with the field insulating film (23). No field electrode is provided on the field insulating film (23).
Japanese Unexamined Patent Application Publication No. 2007-103902 and US Patent Application Publication No. 2007/0052015 which is based on Japanese Unexamined Patent Application Publication No. 2007-103902 disclose a structure in which electric field concentration in an outer peripheral region is alleviated by defining a positional relationship between a p/n junction in the outer peripheral region and an inner end of a field insulating film.
FIG. 1 of Japanese Unexamined Patent Application Publication No. 2007-103902 and FIGS. 1A and 1B of US Patent Application Publication No. 2007/0052015 disclose a structure in which an outer peripheral region (56) has no annular shallow p-type region, and column regions (38) are formed at positions shallower than column regions (34, 36) in an element forming region (54). In the outer peripheral region (56), a field insulating film (46) and a field electrode (48) are stacked immediately above the column regions (38). The column regions (38) are formed under the field insulating film (46) in the outer peripheral region (56). Meanwhile, the column region (38) is not formed immediately below an inner end (64) of the field insulating film (46) and in its neighboring region, thereby alleviating the electric field concentration in the vicinity of the inner end (64) of the field insulating film (46).
FIG. 1 of Japanese Unexamined Patent Application Publication No. 2006-196518 and FIG. 1 of US Patent Application Publication No. 2006/0151831 which is based on Japanese Unexamined Patent Application Publication No. 2006-196518 disclose the following structure. That is, a shallow p-type region (105) and column regions (106) are formed in an outer peripheral region; a field insulating film (118) is formed in a region (a region in which the shallow p-type region (105) and the column regions (106) are not formed) outside an outermost peripheral column region (106a) in the outer peripheral region; and a field electrode (120) is formed in a region excluding portions immediately above the column regions (106) in the outer peripheral region.
In this regard, it is disclosed that the column regions (106a) are formed in the outer peripheral region, thereby maintaining a high breakdown voltage in the outer peripheral region. As disclosed in Japanese Unexamined Patent Application Publication No. 2006-196518 and US Patent Application Publication No. 2006/0151831, the field electrode (120) is not formed immediately above the column region (106a), thereby making it possible to form the column region (106a) after formation of the field electrode.
Japanese Unexamined Patent Application Publication No. 2009-088345 and US Patent Application Publication No. 2009/0090968 which is based on Japanese Unexamined Patent Application Publication No. 2009-088345 are cited for reference as a structure of the type in which the outer peripheral region has no columnar region. FIG. 1 of Japanese Unexamined Patent Application Publication No. 2009-088345 and FIG. 1 of US Patent Application Publication No. 2009/0090968 disclose the following structure. That is, p-type buried semiconductor regions (BGR1 to BGR4) are formed in the outer peripheral region instead of column regions (4); annular shallow p-type regions (GR1 to GR4) are formed above the buried semiconductor regions (BGR1 to BGR4); and a field electrode (14) is formed immediately above the annular shallow p-type regions (GR1 to GR4). Japanese Unexamined Patent Application Publication No. 2009-088345 discloses in paragraphs 0032 to 0041 that the annular shallow p-type regions (GR1 to GR4) and the buried semiconductor regions (BGR1 to BGR4) allow to suppress local electric field concentration.